You can usually make an excuse to squeeze a prototype circuit boards trace between pads on an SOIC. It’s a little tight (you might want to run most of the board with 10 mil (0.4mm) minimum trace width and clearance rules) but it should come out okay (maybe the cheapest board houses will sometimes make a mistake on it).
Beware of built-in library footprints. They almost universally are poor. Chip resistors/capacitors, for instance, have a heel gap (inside space between pads, also the gap between metal connections on the ends) that is often way too high (fails IPC standards = solders poorly) or too small (you can’t even get one trace through). Likewise with SOICs, SOTs, etc., there are all kinds. You can always find footprints from the manufacturers and compare them. PITA, but worth it in the end, and you get a library with parts that meet your preferences.
That’s just the parts that you need for soldering; often, the silkscreen isn’t quite right, or the 3D model data (if present at all) is poor. (If you want a really good looking one, it seems like you have no choice but to go out of your way and make the model yourself in SolidWorks, assuming you can import a compatible format like STEP.) Not that mechanical data (like 3D) is important for good flexible PCB design, but it is helpful for considering the assembly layout, especially if you’re constrained on space in the mechanical design of the project.
it is probably not going to get as many traces underneath a given part, but on the other hand, you can attempt to place all SMT on a single side, which keeps the back side completely clear, and use vias and traces as jumper wires.
If you’re doing handmade boards, you’ll also want to minimize vias.
The circuit was easy to lay out with almost no vias. Only a few are used to tie the local ground (which is a sinuous trace, and ought to be poured like I said) to the back side ground plane, and to route supply voltage. For vias, I used 25 mil holes and 26AWG wire nubs soldered on both sides.