DDR layout in the PCB design occupies a pivotal position, the key point is to ensure that the system has sufficient time margin. To ensure the timing of the system, line length matching is an important part. Let’s look back, the basic principle for DDR wiring, line length matching is: keep the clock the same length as the address, control / command signal and the data signal is equal length to DQS. Why? Maybe you will say in this case the same group signals will reach the receiver at the same time, so that the receiving chip can deal with these signals simultaneously. So, if the clock signal and address reach the receiver at the same, what about the corresponding relationship between the wave forms? Let’s see the specific waveform by simulation.
Establish the following channels, respectively, analog DDR3 address signal and clock signal.

To facilitate the calculation, we assume that the DDR clock frequency is 500MHz, so that the corresponding address signal rate should be 500Mbps, where we should understand that although DDR is double rate, but the address / control signal is still single speed. Then let’s look at the waveform, when the address and the clock is completely the same, the address and the data side of the receiving waveform as shown in Figure 2, red on behalf of the address signal, green is clock signal.

From the above waveforms, it’s barely to see what the relationship between the clock and the address is, and we put it in an eye diagram, and the timing relationship is clear. Here’s a rough calculation of the build time and hold time as following

From the above figure 3. We can know that the address signal settling time is about 891ps, holding time is 881ps. This is the waveform in the case where the clock and address signals are exactly equal. If the address and the clock is not equal, what should be the signal? In the simulation, we let the address line slower than the clock line 200ps, get the following eye diagram:

As we can see from the above picture, when the address signal is longer than the clock signal, the holding time is 684 ps and the establishment is 1.1 ns. It can be seen that comparing with the same length address line and clock line, the address signal will be easier established if the address line is longer than the clock line. Similarly, if the clock line is longer than the address line, the settling time becomes longer and the hold time becomes shorter. Then what about the double rate data signal? Let’s look at the specific simulation as following.
Simulation channel as shown above, the driver and receiver are IBIS models of a chip company. The simulation waveform is as follows:

We generate the eye diagram of DQS and DQ signal at the same time, observed in a window, the results are as follows:

As shown above, we may find that if the edge of the data signal and the edge of the clock signal are aligned in terms of the original correspondence, if so, how does the clock signal complete the sampling of the data signal? In fact, this is not the case. The above simulation is simply to put the two waveforms together, because the DQ and DQS transmission channel length is the same, so their edges are aligned. In the actual work, the master chip will have a regulatory mechanism. The general data signal will be released ahead of a quarter than the DQS be released. In fact, the particles received at the end of the corresponding correspondence should be like this:

After the adjustment of the master chip, the edge of the DQS is aligned with the center of the DQ signal bit, which ensures that the data has sufficient settling time and hold time at the receiver. And the above analysis of the clock and the address signal, if the DQ and DQS wasn’t designed to the equal length, DQS clock edge will not remain in the middle of the DQ, so set the time or keep the time margin will become smaller.

In the figure above, T_vb and T_va represent the timing parameters between the clock and the data when the master chip outputs data. Ideally, the clock edge and the center of the data level are aligned, since the clock and data transmission channels are not equal, so that the clock edge does not have an intermediate position with the data pulse, making the margin of the settling time smaller. After understanding these basic questions, we need to do is to convert these time parameters into line length.
The following figure shows the timing of the calculation, the following figure is Freescale MPC8572 DDR master chip manual, this picture defines the chip out from the time, the relationship between DQS and DQ phase.

The timing of the chip and the timing parameters are shown in the following figure. This picture defines the settling time and hold time required for the chip-side chip to identify the signal.

We use T_pcbskew to represent the delay deviation between DQ and DQS. If you want to get enough time margin, the delay deviation should satisfy the following relationship:
T_pcbskew “T_vb-T_setup
T_pcbskew “T_hold-T_va
Substituting data, there are:
T_vb-T_setup = 375-215 = 160ps
T_hold-T_va = -160ps
Thus, if the speed of the transmission line is calculated at 6 mil / ps, T_pcbskew is +/- 960 mils. We will find a great margin, of course, this is only the best situation, not to consider the clock jitter and data signal jitter, as well as crosstalk, inter-code interference, if these factors are taken into account, leaving us wiring deviation Margin is relatively small.
To sum up, the purpose of timing control is to ensure that the data at the receiving end has sufficient time to build and maintain time, understand this, we will be able to match the problem on the line can be done.